1. Fiend of the Invention
The present invention generally relates to analog-to-digital converters (ADCs), and more particularly to a stage-resolution scalable opamp-sharing technique adaptable for pipelined ADCs or cyclic ADCs that can substantially reduce the amount of operational amplifiers and associated power consumption, and increase operating speed.
2. Description of the Prior Art
Growing demands for portable communication and audio/video electronic devices call for longer operating times. Battery power alone, however, cannot keep up with the pressing need for longer operating time. Reducing power consumption is thus becoming an alternative and more feasible way to reach the object of augmenting the operating times for such devices.
The pipelined analog-to-digital converter (ADC) is widely utilized, over other ADC architectures, in video applications for the reason that its hardware requirement linearly increases with the associated resolution, instead of the exponential increases associated with flash ADC architectures. For applications with 10 bits of resolution, for example, the hardware requirement, and accordingly the required silicon area and power consumption, of the pipelined ADC are substantially lower than other ADC architectures.
FIG. 1 illustrates a conventional pipelined ADC architecture 1. The input signal Vin is first sampled by a front-end sample-and-hold amplifier (SHA) 11, which then provides a stably held signal to a later stage 12. Each stage 12 performs a portion of bits (B) of conversion, respectively. The converted bits are synchronized by delay elements 13, and then corrected and integrated by a digital error correction logic 14, finally outputting a complete N-bit code, where N is the ADC resolution. As shown in the expanded block, each stage 12 includes a sub-ADC 121, a sub-DAC (digital-to-analog converter) 122, a SHA 123, an analog subtractor 124 and an amplifier (Gi) 125. The sub-ADC 121 of each stage 12 performs coarse quantization on its corresponding input signal to generate a portion of bits, which is then converted into associated analog voltage by the sub-DAC 122. The converted analog voltage is subsequently subtracted from the sampled input signal by the subtractor 124, resulting in residual signal 126 which represents quantization error of the input signal through the associated stage 12. The residual signal 126 is then amplified by the amplifier 125, such that the value of the residual signal 126 is within the signal range of the overall ADC 1. Accordingly, the reference voltage can be shared among the stages 12, thereby simplifying the system design. Further, as the bits of resolution become less through more stages while the signal range is maintained, later stages therefore have a precision requirement less stringent than preceding stages.
FIG. 2 illustrates an implementation of a multiplying DAC (MDAC) 120 consisting of the sub-DAC 122, the SHA 123, the analog subtractor 124 and the amplifier (Gi) 125 (such as an operational amplifier or opamp). The MDAC 120 is implemented, in this example, with a switched-capacitor circuit as connected, and performs 1.5 bits of conversion in each stage (i.e., 1.5-bit/stage). When clock clk1 becomes high (“1”), the MDAC 120 enters into sample phase, the amplifier 125 has a unity gain configuration and the offset (Vos) of the amplifier 125 is stored in the upper plates of the capacitors Cf and Cs (near the input node of the amplifier 125). Subsequently, when clock clk2 becomes high (“1”), the MDAC 120 enters into amplify phase, the capacitor Cf acts as feedback capacitor and the bottom plate of the capacitor Cs is connected to the output voltage VR of the sub-DAC 122, thereby amplifying the residual signal and correcting the offset in this phase. The precision of the MDAC 120 determines the precision of the overall ADC 1, while the precision of the MDAC 120 itself is determined by the effective parameters, such as gain and bandwidth, of the amplifier 125. In addition, as the amplifiers 125 consume considerable power in the overall ADC 1, making effort to reduce the power consumption in the amplifiers 125 becomes critical in substantially reducing power consumption in the overall ADC 1. Further, as later stages have precision requirements less stringent than preceding stages, amplifiers 125 with lower gain and bandwidth may be used to substantially reduce the power consumption. Nevertheless, this requires designing variety of or among amplifiers, which translates into more circuit design time.
In general, as the pipelined ADC 1 with the digital error correction logic 14 can tolerate considerable offset, the offset of the amplifiers 125 will not substantively affect the linearity characteristics of the overall ADC 1, provided that the offset does not exceed the tolerable range of the digital error correction logic 14. Accordingly, the MDAC 120 does not need offset correction. Therefore, when the clock clk1 becomes high (“1”), there is no need to set up the amplifier 125 in a unity gain configuration to store the offset. In other words, the amplifier 125 is idle in the sample phase as shown in FIG. 3. The capability of utilizing the idle amplifier 125 in the sample phase will further reduce the overall power consumption as disclosed in the following techniques.
(1) Double-Sampling Technique
FIG. 4 illustrates a two-channel time-interleaved architecture 4, which is used to accelerate the overall ADC operation. As the sample phase and amplify phase are time-interleaved, that is, one channel 40 is under sampling while the other channel 41 is under amplifying, the two channels will not use the (operational) amplifier 42 at the same time. Accordingly, the amplifier 42 can be shared, such that the operating speed of each stage can be doubled, or, in other words, the bandwidth of the amplifier 42 can be reduced in half, thereby substantially reducing power consumption. Despite the advantages mentioned above, this technique nevertheless requires an additional pair of capacitors (or more silicon area) for switching between the channels. Further, more circuits, and thus more power consumption and silicon area, are required to cope with channel mismatch issues, such as timing mismatch, offset mismatch and gain mismatch.
(2) Opamp Sharing Technique
As the operation of the two neighboring stages in a pipelined ADC is also interleaved, that is, one stage is under sampling while another neighboring stage is under amplifying, the two neighboring stages may share an opamp to reduce the power consumption in half, as shown in FIG. 5. The ADC 5 shown in FIG. 5 adopts the same stage-resolution for every pipelined stage. Thus, the accuracy requirement of the shared amplifier 52 needs to conform to that of the former stage. Since the precision requirement of the later stage (e.g., stage 2) in general is less stringent than that of the preceding stage (e.g., stage 1), sharing of the preceding-stage's amplifier 52 with the later stage is disadvantageous and wasteful. The opamp sharing technique consumes more power than the double-sampling technique for the reason that the double-sampling technique can reduce the bandwidth in half and be optimized according to the precision requirement in each stage. On the contrary, the opamp sharing technique avoids channel mismatch issues and associated correction scheme and circuit design complexity compared with the double-sampling technique.
For the reason that the above-mentioned conventional ADC architectures have respective disadvantages, a need has arisen to propose a novel ADC architecture that can maintain the advantages while avoid the disadvantages of conventional ADC architectures.